| Electronic component: | Description: | Manuf. | Package | Pins | T°min | T°max | Datasheet |
|---|
| DM74LS73ACW | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs | Fairchild-Semiconductor | - | - | - | - | 53 K |
| DM74LS73AM | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs | Fairchild-Semiconductor | SOIC | 14 | - | - | 53 K |
| DM74LS73AN | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs | Fairchild-Semiconductor | MDIP | 14 | - | - | 53 K |
| DM74LS74ACW | Dual Positive-Edge-Triggered D Flip-Flop with Preset Clear and Complementrary Outputs | Fairchild-Semiconductor | - | - | - | - | 67 K |
| DM74LS74AM | Dual Positive-Edge-Triggered D Flip-Flop with Preset Clear and Complementrary Outputs | Fairchild-Semiconductor | SOIC | 14 | - | - | 67 K |
| DM74LS74AMX | Dual Positive-Edge-Triggered D Flip-Flop with Preset Clear and Complementrary Outputs | Fairchild-Semiconductor | SOIC | 14 | - | - | 67 K |
| DM74LS74AN | Dual Positive-Edge-Triggered D Flip-Flop with Preset Clear and Complementrary Outputs | Fairchild-Semiconductor | MDIP | 14 | - | - | 67 K |
| DM74LS74ASJ | Dual Positive-Edge-Triggered D Flip-Flop with Preset Clear and Complementrary Outputs | Fairchild-Semiconductor | SOIC | 14 | - | - | 67 K |
| DM74LS74ASJX | Dual Positive-Edge-Triggered D Flip-Flop with Preset Clear and Complementrary Outputs | Fairchild-Semiconductor | SOIC | 14 | - | - | 67 K |
| DM74LS75M | Quad Latch | Fairchild-Semiconductor | SOIC | 16 | - | - | 49 K |
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