| Electronic component: | Description: | Manuf. | Package | Pins | T°min | T°max | Datasheet |
|---|
| GCL10-B | 9.8 KN clamp for press pack device | distributor | - | - | - | - | 837 K |
| GCL10-BS | 9.8 KN clamp for press pack device | distributor | - | - | - | - | 837 K |
| MACH210-12JC | High-density EE CMOS programmable logic, 64 macrocells, 32 outputs, 38 Inputs, 64 flip-flops; 2 clock choices, 12ns | Lattice-Semiconductor-Corporation | PLCC | 44 | 0°C | 70°C | 347 K |
| MACH210-15JC | High-density EE CMOS programmable logic, 64 macrocells, 32 outputs, 38 Inputs, 64 flip-flops; 2 clock choices, 15ns | Lattice-Semiconductor-Corporation | PLCC | 44 | 0°C | 70°C | 347 K |
| MACH210-20JC | High-density EE CMOS programmable logic, 64 macrocells, 32 outputs, 38 Inputs, 64 flip-flops; 2 clock choices, 20ns | Lattice-Semiconductor-Corporation | PLCC | 44 | 0°C | 70°C | 347 K |
| MACHLV210-12JC | High density EE CMOS programmable logic, 64 macrocells, 32 outputs, 64 flip-flops; 2 clock choices, 12ns | Lattice-Semiconductor-Corporation | PLCC | 44 | 0°C | 70°C | 221 K |
| MACHLV210-15JC | High density EE CMOS programmable logic, 64 macrocells, 32 outputs, 64 flip-flops; 2 clock choices, 15ns | Lattice-Semiconductor-Corporation | PLCC | 44 | 0°C | 70°C | 221 K |
| MACHLV210-18JI | High density EE CMOS programmable logic, 64 macrocells, 32 outputs, 64 flip-flops; 2 clock choices, 18ns | Lattice-Semiconductor-Corporation | PLCC | 44 | -40°C | 85°C | 221 K |
| MACHLV210-20JC | High density EE CMOS programmable logic, 64 macrocells, 32 outputs, 64 flip-flops; 2 clock choices, 20ns | Lattice-Semiconductor-Corporation | PLCC | 44 | 0°C | 70°C | 221 K |
| MACHLV210-24JI | High density EE CMOS programmable logic, 64 macrocells, 32 outputs, 64 flip-flops; 2 clock choices, 24ns | Lattice-Semiconductor-Corporation | PLCC | 44 | -40°C | 85°C | 221 K |
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