Electronic component: | Description: | Manuf. | Package | Pins | T°min | T°max | Datasheet |
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74VHC112CW | Dual J-K Flip-Flops with Preset and Clear | Fairchild-Semiconductor | - | - | - | - | 70 K |
74VHC112M | Dual J-K Flip-Flops with Preset and Clear | Fairchild-Semiconductor | SOIC | 16 | - | - | 70 K |
74VHC112MTC | Dual J-K Flip-Flops with Preset and Clear | Fairchild-Semiconductor | TSSOP | 16 | - | - | 70 K |
74VHC112MTCX | Dual J-K Flip-Flops with Preset and Clear | Fairchild-Semiconductor | TSSOP | 16 | - | - | 70 K |
74VHC112MTCX | Dual J-K Flip-Flops with Preset and Clear | Fairchild-Semiconductor | TSSOP | 16 | - | - | 70 K |
74VHC112N | Dual J-K Flip-Flops with Preset and Clear | Fairchild-Semiconductor | MDIP | 16 | - | - | 70 K |
74VHC112SJ | Dual J-K Flip-Flops with Preset and Clear | Fairchild-Semiconductor | SOIC | 16 | - | - | 70 K |
74VHC112SJX | Dual J-K Flip-Flops with Preset and Clear | Fairchild-Semiconductor | SOIC | 16 | - | - | 70 K |
DM74LS112AM | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop | Fairchild-Semiconductor | SOIC | 16 | - | - | 52 K |
DM74LS112AMX | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop | Fairchild-Semiconductor | SOIC | 16 | - | - | 52 K |
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