Electronic component: | Description: | Manuf. | Package | Pins | T°min | T°max | Datasheet |
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ISPLSI3256-50LG | High density programmable logic, 128 I/O pins, 11000 PLD gates, 384 registers, 57MHz | Lattice-Semiconductor-Corporation | CPGA | 167 | 0°C | 70°C | 1 M |
ISPLSI3256-70LG | High density programmable logic, 128 I/O pins, 11000 PLD gates, 384 registers, 77MHz | Lattice-Semiconductor-Corporation | CPGA | 167 | 0°C | 70°C | 1 M |
ISPLSI3256E-100LB320 | In-system programmable high density PLD, 256 I/O pins, 12000 PLD gates, 512 registers, 100MHz | Lattice-Semiconductor-Corporation | BGA | 320 | 0°C | 70°C | 159 K |
ISPLSI3256E-100LQ | In-system programmable high density PLD, 256 I/O pins, 12000 PLD gates, 512 registers, 70MHz | Lattice-Semiconductor-Corporation | PQFP | 304 | 0°C | 70°C | 159 K |
ISPLSI3256E-70LB320 | In-system programmable high density PLD, 256 I/O pins, 12000 PLD gates, 512 registers, 70MHz | Lattice-Semiconductor-Corporation | BGA | 320 | 0°C | 70°C | 159 K |
ISPLSI3256E-70LQ | In-system programmable high density PLD, 256 I/O pins, 12000 PLD gates, 512 registers, 70MHz | Lattice-Semiconductor-Corporation | PQFP | 304 | 0°C | 70°C | 159 K |
PLSI3256-50LG | High density programmable logic, 128 I/O pins, 11000 PLD gates, 384 registers, 57MHz | Lattice-Semiconductor-Corporation | CPGA | 167 | 0°C | 70°C | 1 M |
PLSI3256-70LG | High density programmable logic, 128 I/O pins, 11000 PLD gates, 384 registers, 77MHz | Lattice-Semiconductor-Corporation | CPGA | 167 | 0°C | 70°C | 1 M |
TMS4256-12NE | 262144-bit dynamic random-access memory, 120ns | Texas-Instruments | DIP | 16 | -40°C | 85°C | 1 M |
TMS4256-12NE | 262144-bit dynamic random-access memory, 120ns | Texas-Instruments | DIP | 16 | -40°C | 85°C | 1 M |
TMS4256-15NE | 262144-bit dynamic random-access memory, 150ns | Texas-Instruments | DIP | 16 | -40°C | 85°C | 1 M |
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