Electronic component: | Description: | Manuf. | Package | Pins | T°min | T°max | Datasheet |
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TEA1064B | Low voltage versatile telephone transmission circuit with dialler interface and transmit level dynamic limiting | Philips-Semiconductors | DIP | 20 | -25°C | 70°C | 167 K |
uPD45128163G5-A10-9JF | 128M-bit synchronous DRAM, organization 2M x 16 x 4, LVTTL, 10ns, 3.3V | distributor | TSOP II | 54 | 0°C | 70°C | 682 K |
uPD45128163G5-A10LT-9JF | 128M-bit (2M x 16-bit x 4-bank), synchronous DRAM LVTTL, 100 MHz | distributor | TSOP II | 54 | -20°C | 85°C | 713 K |
uPD45128163G5-A10T-9JF | 128M-bit (2M x 16-bit x 4-bank), synchronous DRAM LVTTL, 100 MHz | distributor | TSOP II | 54 | -20°C | 85°C | 713 K |
uPD45128441G5-A10-9JF | 128M-bit synchronous DRAM, organization 8M x 4 x 4, LVTTL, 10ns, 3.3V | distributor | TSOP II | 54 | 0°C | 70°C | 682 K |
uPD45128441G5-A10LT-9JF | 128M-bit (8M x 4-bit x 4-bank), synchronous DRAM LVTTL, 100 MHz | distributor | TSOP II | 54 | -20°C | 85°C | 713 K |
uPD45128441G5-A10T-9JF | 128M-bit (8M x 4-bit x 4-bank), synchronous DRAM LVTTL, 100 MHz | distributor | TSOP II | 54 | -20°C | 85°C | 713 K |
uPD45128841G5-A10-9JF | 128M-bit synchronous DRAM, organization 4M x 8 x 4, LVTTL, 10ns, 3.3V | distributor | TSOP II | 54 | 0°C | 70°C | 682 K |
uPD45128841G5-A10LT-9JF | 128M-bit (4M x 8-bit x 4-bank), synchronous DRAM LVTTL, 100 MHz | distributor | TSOP II | 54 | -20°C | 85°C | 713 K |
uPD45128841G5-A10T-9JF | 128M-bit (4M x 8-bit x 4-bank), synchronous DRAM LVTTL, 100 MHz | distributor | TSOP II | 54 | -20°C | 85°C | 713 K |
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