The TLC556 datasheet

Caffy · Guru Joined: Nov 06, 2009 Posts: 93

The TLC556 has some features,(1)Very Low Power Consumption:2mW Typ at VDD=5V;(2)Capable of Operation in Astable Mode;(3)CMOS Output Capable of Swinging Rail to Rail;(4)High Output-Current Capability;(5)Output Fully Compatible With CMOS, TTL,and MOS;(5)Low Supply Current Reduces Spikes During Output Transition;(6)Single-Supply Operation From 2V to 15V;(7)Functionally interchangeable With the NE556; Has Same Pinout.
The TLC556 series are monolithic timing circuits fabricated using the TI LinCMOSE process, which provides full compatibility with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Accurate time delays and oscillations are possible with smaller, less-expensive timing capacitors than the NE556 because of the high input impedance. Power consumption is low across the full range of power supply voltage.
http://www.seekic.com/icdata/The_TLC556.html
Like the NE556, the TLC556 has a trigger level approximately one-third of the supply voltage and a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high.If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal and ground.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC556 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the NE556.These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015. However, care should be exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric performance. All unused inputs should be tied to an appropriate logic level to prevent false triggering.